IBM Works With European Union to Improve Productivity of Chip Designs

Engineering & Technology Services Division to Offer New Tools That Help Reduce Time to Market

Munich, Germany, March 8, 2005 -- IBM announced today at the DATE technical conference here that a collaborative effort among several European companies, universities and the European Union to change the way microchips are designed has produced advanced technologies which could improve chipmaking productivity by up to 30 percent.

The EU last year awarded 7 million Euros to a consortium of three companies and four universities with the purpose of encouraging the development and deployment of new tools and methodologies that will increase chip design productivity and reduce time to market.

The collaborative research effort -- known as Prosyd -- is centred around a specification language known as PSL and PSL-based tools and methodologies. PSL, based on the Sugar language from IBM, is a powerful, concise language for assertion specification and complex modelling. As an emerging standard, PSL provides an interoperation language that enables engineers to exchange hardware specifications and develop seamless tool integration.

The key result of the joint investment so far is in an impressive collection of tools developed by the members of the Consortium which interoperate around the emerging PSL standard. In particular, the IBM tools provide powerful PSL-based solutions for the vital process of chip verification; that is, the demanding need to ensure that every one of the millions and millions of individual chip circuits actually work according to spec.

"The new IBM tools incorporate the use of the PSL standard, which together with advanced algorithms is opening up new directions in formal verification of larger designs," said Moshe Molcho, who manages IBM's Haifa Development Lab. "Engineers can now reduce development costs, design higher quality electronic systems, and offer them to customers faster than in the past by including these tools into the way they do business."

IBM will offer the tools in Europe through IBM Engineering & Technology Services, a well-established 'engineering on demand' business unit with such well-known clients as Boeing, Honeywell, Sony, Microsoft, and many others. Some of the industry-first PSL-based tools and methodologies being offered by IBM E&TS in Europe include the IBM DV RuleBase PE and IBM DV FoCs assertion compiler, developed at the IBM Haifa Research Lab as part of the Prosyd project. RuleBase PE is a formal verification solution which exhaustively checks all possible behaviors of the chip while still on the designer's desk, and offers a mathematical guarantee for their validity while leveraging parallel computing techniques. The FoCs assertion compiler translates PSL assertions into HDL checkers, which are integrated into the simulation environment. These checkers monitor chip simulation results on a cycle-by-cycle basis for violation of assertions.

"We foresee ample innovations in chip design and verification made possible using the property-based design and verification techniques enabled by Prosyd," says Dieter Muenk, General Manager of E&TS for IBM in Europe. "This new offering demonstrates IBM's continued commitment to serving our customers by rapidly bringing state-of-the-art design and verification technologies to the marketplace."

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